The present invention relates to integrated circuit technology. More particularly, the present invention relates to user programmable integrated circuits and to lookup table MODULESs (LUTs) used to configure circuit elements in user programmable integrated circuits.
LUTs are widely employed in user programmable integrated circuits A four-input LUT (LUT4) module is employed in user programmable field programmable gate array (FPGA) products, such as the ones designed and marketed by Microsemi SoC Corp., assignee of the present invention. A typical LUT4 module is shown in FIG. 1 and consists of four ranks of multiplexers configured in a tree structure. A first rank of eight 2-input multiplexers have their data inputs coupled to programmable constants, which determine the combinatorial logic of the LUT4. The first-rank multiplexers each have their select inputs coupled to a “D” input of the LUT4 module. A second rank of four 2-input multiplexers have their data inputs coupled to the outputs of an adjacent pair of the multiplexers of the first rank. The second rank multiplexers each have their select inputs coupled to a “C” input of the LUT4 module. The routing architecture for LUT4 circuits is well understood. A third rank of two 2-input multiplexers have their data inputs coupled to the outputs of an adjacent pair of the multiplexers of the second rank. The third rank multiplexers each have their select inputs coupled to a “B” input of the LUT4 module. A fourth rank of a single 2-input multiplexer has its data inputs coupled to the outputs of an adjacent pair of the multiplexers of the third rank. The fourth rank multiplexer has its select input coupled to an “A” input of the LUT4 module. The output of the fourth rank multiplexer is the output Y of the LUT4 module. The routing architecture for LUT4 module circuits is well understood.
Two LUT4 modules are required to configure a 4-input multiplexer (MUX4) circuit, as illustrated in FIG. 2. In the left portion of FIG. 2 a, combinatorial arrangement of a first LUT40 implements a first portion of the 4-input multiplexer is shown. Each of inputs A-D are denoted with a postscript “0” for clarity. A second combinatorial arrangement, representing a second portion of the 4-input multiplexer, implemented by a second LUT41, is shown adjacent the first LUT40, with each of the inputs A-D of the second LUT41, denoted with a postscript “1” for clarity. By connecting the output of LUT4 0, i.e, Y0, as the A1 input of LUT4 1, a 4-input multiplexer is formed as shown in the right two illustrations. For clarity, the select inputs of the 4-input multiplexer are denoted S0 and S1. It can be seen that select input S0 is formed by input A0, and select input S1 is formed by B0, B1, i.e. inputs B0 and B1 are tied together. In accordance with the naming convention used herein, the data inputs of the user-configured 4-input multiplexer are denoted U0, U1, U2 and U3 and their equivalents in the initial LUT4 implementations are shown (i.e. U0 is formed by C0; U1 is formed by C1; U2 is formed by C1 and U3 is formed by D1. This arrangement is relatively inefficient. The output of the user-implemented 4-input multiplexer is designated by X.
Six-input LUT modules (LUT6) are used in some FPGA integrated circuits. The use of LUT6 modules allows a MUX4 to be configured in one LUT6. A typical LUT6 module is shown in FIG. 3. A first LUT4 (LUT40) module is shown within dashed lines in FIG. 3. The outputs of LUT40 as well as from three additional LUT4 modules (LUT41, LUT42, and LUT43) are shown combined in a fifth rank of multiplexers, each having their select inputs coupled to the “B” input. The output Y of the LUT6 module is taken from the sixth rank multiplexer having the “A” input coupled to its select input. An equivalent circuit of the user-implemented 4-input multiplexer of the LUT6 module is shown in FIG. 4, with the data inputs of the 4-input multiplexer, denoted U0, U1, U2 and U3, the select inputs S1 and S0, with their equivalent inputs in the LUT6 identified, and the output identified as X, and is formed by output Y1.
A major drawback of a LUT6 module is that it occupies more than three times the area of a LUT4 module. In addition, a LUT6 module requires the use of four times as many configuration memory cells as a LUT4 module, and can be up to 40% slower than a LUT 4 module. A LUT6 module utilizes more than 50% more routing area than a LUT4 module.
Other disadvantages of a LUT6 module include an overall module-cost of about 1.75 times that of a LUT4-module, and an average LUT6 module count requirement of about 1.6 times that of a LUT4 module. Because of these and other disadvantages, it is desired to find an alternative to the use of a LUT6 module that will be efficient for configuring MUX4 circuits without the high area and performance penalties of LUT6 modules.